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1 ds05-10165-3e fujitsu semiconductor data sheet memory cmos 1 m 16 bit fast page mode dynamic ram mb8116160a-60/-70 cmos 1,048,576 16 bit fast page mode dynamic ram n description the fujitsu mb8116160a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 16-bit increments. the mb8116160a features a ?ast page mode of operation whereby high- speed random access of up to 256-bits of data within the same row can be selected. the mb8116160a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb8116160a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb8116160a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb8116160a are not critical and all inputs are ttl compatible. n product line & features parameter mb8116160a-60 MB8116160A-70 ras access time 60 ns max. 70 ns max. random cycle time 110 ns min. 130 ns min. address access time 30 ns max. 35 ns max. cas access time 15 ns max. 17 ns max. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 550 mw max. 495 mw max. standby current 11 mw max. (lvttl level) / 5.5 mw max. (cmos level) 1,048,576 words 16 bit organization silicon gate, cmos, advanced capacitor cell all input and output are ttl compatible 4096 refresh cycles every 65.6ms self refresh function early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb8116160a-60/MB8116160A-70 n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7.0 v voltage of v cc supply relative to v ss v cc ?.5 to +7.0 v power dissipation p d 1.0 w short circuit output current 50 ma operating temperature t ope 0 to 70 c storage temperature t stg ?5 to +125 c (lcc-42p-m01) plastic soj package (fpt-50p-m06) plastic tsop package package and ordering information ?42-pin plastic (400mil) soj, order as mb8116160a- pj ?50-pin plastic (400mil) tsop-ii with normal bend leads, order as mb8116160a- pftn (normal bend)
3 mb8116160a-60/MB8116160A-70 n capacitance (t a =25 c, f = 1mhz) parameter symbol max. unit input capacitance, a 0 to a 11 c in1 5pf input capacitance, ras , lcas , ucas , we , oe c in2 5pf input/output capacitance, dq 1 to dq 16 c dq 7pf fig. 1 ?mb8116160a dynamic ram ?block diagram mode control write clock gen ras lcas ucas clock gen #2 data in buffer we dq 1 to dq 16 oe v cc v ss data out buffer column decoder clock gen #1 sense ampl & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder refresh address counter row decoder substrate bias gen a 2 a 1 a 4 a 3 a 6 a 5 a 8 a 7 a 10 a 9 a 0 a 11
4 mb8116160a-60/MB8116160A-70 n pin assignments and descriptions 1 pin index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 21 22 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 21 30 22 29 23 28 24 27 25 26 designator function a 0 to a 11 address inputs row : a 0 to a 11 column : a 0 to a 7 refresh : a 0 to a 11 row address strobe ras lower column address strobe upper column address strobe write enable output enable data input/output circuit ground no connection +5.0 volt power supply lcas ucas we oe dq 1 to dq 16 v cc v ss n.c. v cc dq 1 dq 2 dq 3 dq 4 v ss v ss dq 16 dq 15 dq 14 dq 13 we ras a 11 a 10 a 0 a 1 a 2 a 3 v cc v ss dq 12 a 9 a 8 a 7 a 6 a 5 a 4 42-pin soj (top view) dq 11 dq 10 dq 9 lcas ucas oe n.c. n.c. n.c. v cc dq 5 dq 6 dq 7 dq 8 we ras a 11 a 10 a 0 a 1 a 2 a 3 v cc n.c. n.c. v cc dq 1 dq 2 dq 3 dq 4 n.c. v cc dq 5 dq 6 dq 7 dq 8 v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 n.c. v ss a 9 a 8 a 7 a 6 a 5 a 4 lcas ucas oe n.c. 1 pin index 50-pin tsop (top view)
5 mb8116160a-60/MB8116160A-70 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. since only twelve address bits (a0 to a11) are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 1. first, twelve row address bits are input on pins a0-through-a11 and latched with the row address strobe (ras ) then, eight column address bits are input and latched with the column address strobe (lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are of the ?w-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways-an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or lcas / ucas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data of dq1-dq8 is strobed by lcas and dq9-dq16 is strobed by ucas and the setup/hold times are referenced to each lcas and ucas because we goes low before lcas / ucas . in a delayed write or a read-modify-write cycle, we goes low after lcas / ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signa data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of lcas (for dq1-dq8) ucas (for dq9-dq16) when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa , and t rcd (max) is satis?d. the data remains valid until either lcas / ucas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 256x16-bits can be accessed and, when multiple mb8116160as are used, cas is decoded to select the desired memory fast page. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage v cc 4.5 5.0 5.5 v 0 c to + 70 c v ss 000 input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs* v il ?.0 0.8 v 1 1 1
6 mb8116160a-60/MB8116160A-70 n dc characteristics (recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol condition values unit min. typ. max. output high voltage v oh i oh = ?.0 ma 2.4 v output low voltage v ol i ol = +4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in v cc ; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i dq(l) 0v v out v cc ; data out disabled ?0 10 operating current (average power supply current) mb8116160a-60 i cc1 ras & lcas , ucas cycling; t rc = min ma MB8116160A-70 standby current (power supply current) ttl level i cc2 ras = lcas , ucas = v ih ma cmos level ras = lcas , ucas 3 v cc ?0.2 v refresh current #1 (average power supply current) mb8116160a-60 i cc3 lcas , ucas = v ih , ras cycling; t rc = min ma MB8116160A-70 fast page mode current mb8116160a-60 i cc4 ras = v il, lcas , ucas cycling; t pc = min ma MB8116160A-70 refresh current #2 (average power supply current) mb8116160a-60 i cc5 ras cycling; cas -before-ras ; t rc = min ma MB8116160A-70 refresh current #3 (average power supply current) mb8116160a-60 i cc9 ras = v il , cas = v il self refresh; t rass = min 1000 m a MB8116160A-70 1 1 2 100 90 2.0 1.0 2 100 90 2 90 80 2 90 80
7 mb8116160a-60/MB8116160A-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb8116160a-60 MB8116160A-70 unit min. max. min. max. 1 time between refresh t ref 65.6 65.6 ms 2 random read/write cycle time t rc 110 130 ns 3 read-modify-write cycle time t rwc 150 174 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?5?7ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 3?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time t off ?5?7ns 10 transition time t t 350350ns 11 ras precharge time t rp 40?0ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 15?7ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time t rcd 20 45 20 53 ns 16 cas pulse width t cas 15?7ns 17 cas hold time t csh 60?0ns 18 cas precharge time (normal) t cpn 10?0ns 19 row address set up time t asr 0?ns 20 row address hold time t rah 10?0ns 21 column address set up time t asc 0?ns 22 column address hold time t cah 15?5ns 23 column address hold time from ras t ar 35?5ns 24 ras to column address delay time t rad 15 30 15 35 ns 25 column address to ras lead time t ral 30?5ns 26 column address to cas lead time t cal 30?5ns 27 read command set up time t rcs 0?ns 28 read command hold time referenced to ras t rrh 0?ns 29 read command hold time referenced to cas t rch 0?ns 30 write command set up time t wcs 0?ns 31 write command hold time t wch 15?5ns 6, 9 7, 9 8, 9 10 11, 12 19 13 14 14 15, 20
8 mb8116160a-60/MB8116160A-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb8116160a-60 MB8116160A-70 unit min. max. min. max. 32 write hold time from ras t wcr 35?5ns 33 we pulse width t wp 15?5ns 34 write command to ras lead time t rwl 15?7ns 35 write command to cas lead time t cwl 15?7ns 36 din set up time t ds 0?ns 37 din hold time t dh 15?5ns 38 data hold time from ras t dhr 35 35 ns 39 ras to we delay time t rwd 80?2ns 40 cas to we delay time t cwd 35?9ns 41 column address to we lead time t awd 50?7ns 42 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 43 cas set up time for cas -before-ras refresh t csr 0?ns 44 cas hold time for cas -before-ras refresh t chr 10?2ns 45 access time from oe t oea ?5?7ns 46 output buffer turn off delay from oe t oez ?5?7ns 47 oe to ras lead time for valid data t oel 10?0ns 48 oe hold time referenced to we t oeh 5?ns 49 oe to data in delay time t oed 15?7ns 50 cas to data in delay time t cdd 15?7ns 51 din to cas delay time t dzc 0?ns 52 din to oe delay time t dzo 0?ns 60 fast page mode ras pulse width t rasp 100000 100000 ns 61 fast page mode read/writecycle time t pc 40?5ns 62 fast page mode read-modify-write cycle time t prwc 80?9ns 63 access time from cas precharge t cpa ?5?0ns 64 fast page mode cas precharge time t cp 10?0ns 65 fast page mode ras hold time from cas precharge t rhcp 35?0ns 66 fast page mode cas precharge to we delay time t cpwd 55?2ns 20 20 20 9 10 16 17 17 9, 18
9 mb8116160a-60/MB8116160A-70 notes: 1. referenced to v ss . 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il , ucas = v ih ,lcas = v ih and v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and ucas = v ih ,lcas = v ih . i cc2 is speci?d during ras = v ih and v il > ?.3 v. 3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 5 ns. 5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min) and v il (max). 6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. 7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa ?t cac t t , access time is t cac . 8. if t rad 3 t rad (max) and t asc t aa ?t cac t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 50 pf. 10. t off and t oez is speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min) = t rah (min) + 2 t t + t asc (min). 13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. 16. assumes that t wcs < t wcs (min). 17. either t dzc or t dzo must be satis?d. 18. t cpa is access time from the selection of a new column address (that is caused by changing ucas and lcas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). 19. assumes that cas -before-ras refresh. 20. t wcs , t cwd, t rwd, t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and d out pin will maintain high impedance state through-out the entire cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral speci?ations.
10 mb8116160a-60/MB8116160A-70 n functional truth table x; ? or ? *; it is impossible in fast page mode. operation mode clock input address input/output data refresh note ras lcas ucas we oe row column dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes* cas -before- ras refresh cycle l l l x x high-z high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l l h l h l l h ? xl valid high-z valid high-z valid valid yes previous data is kept. fig. 2 ?t rac vs. t rcd fig. 4 ?t cpa vs. t cp fig. 3 ?t rac vs. t rad t rcd (ns) t rad (ns) t cp (ns) t rac (ns) t rac (ns) t cpa (ns) 60 40 100 80 120 20 060 40 100 80 60ns version 60 50 80 70 90 20 040 30 60 50 40 30 60 50 70 10 030 20 50 40 70ns version 60ns version 70ns version 60ns version 70ns version
11 mb8116160a-60/MB8116160A-70 t rc t ras t ar t crp t csh t rcd t rsh t rp t cas t cdd t oel t ral t cal t cah t asc t rad t rah t asr t rcs t rrh t rch t oh t off t aa t cac t rac t dzc t on t oea t oez t oh t oed t on t dzo row add column add high-z a 0 to a 10 lcas or ucas v ih v il v ih v il we v oh v ol ras v ih v il v ih v il dq (output) v ih v il dq (input) v ih v il oe ? or ? description to implement a read operation, a valid address is latched by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. lcas controls the input/output data on dq1-dq8 pins, ucas controls one on dq8-dq16 pins. the access time is determined by ras (t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas / ucas or oe goes high, the output returns to a high-impedance state after t oh is satisfied. fig. 5 ?read cycle high-z
12 mb8116160a-60/MB8116160A-70 a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) ? or ? description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be imple- mented in either of three ways - early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. fig. 6 ?early write cycle (oe = ??or ?? t rc t ras t rp t crp t csh t rcd t rsh t cas t ar t asr t rah t asc t cah t wcr t wcs t wch t dhr t ds t dh row add column add high-z valid data in lcas or ucas v ih v il
13 mb8116160a-60/MB8116160A-70 lcas or ucas v ih v il a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) ? or ? description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 ?delayed write cycle valid invalid data high-z high-z high-z data i n col add col add v ih v il oe t rc t ras t csh t cas t rsh t rp t rcd t crp t asr t rah t asc t cah t rcs t wch t cwl t rwl t wp t ds t dh t dzc t on t oed t dzo t on t oez t oeh
14 mb8116160a-60/MB8116160A-70 a 0 to a 11 v ih v il v ih v il we v oh v ol ras v ih v il dq (output) v ih v il dq (input) ? or ? description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read-modify- write cycle, oe must be changed from low to high after the memory access time. fig. 8 ?read-modify-write cycle v ih v il oe row add col add valid data i n valid high-z t rwc t ras t crp t rcd t rp t rad t asr t rah t asc t cah t rwd t rcs t awd t cwd t cwl t rwl t wp t dh t ds t dzc t oed t cac t aa t rac high-z t on t oea t oeh t oez t dzo t on t oh high-z lcas or ucas v ih v il
15 mb8116160a-60/MB8116160A-70 description the fast page mode of operation permits faster sucessive memory operations at multiple column locations of the same row address. this operations is performed by strobing in the row address and maintaining ras at a low level and we at a hight level druing all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , which ever one is the lastest in occurring. ras v ih v il we v ih v il dq (output) v oh v ol fig. 9 ?fast page mode read cycle t rasp t rhcp t rcd t rp t rsh t crp t rad t cas t csh t cp t cas t rah t cah t asc t asc t cah t cah t rrh t asc t ral t rcs t rch t rcs t rch t cdd t rcs t rch t on t aa t off t cac t dzc t aa t oh t oh t cac t off t dzc t cpa t oel t dzc t dzo t on t dzo t oez t oea t oez t oea t oed t oed dq (input) v ih v il oe v ih v il col add row add col add col add ? or ?l valid data t asr a 0 to a 11 v ih v il high-z high-z t pc t cas t ar t oh t dzo t oh high-z high-z t rac lcas or ucas v ih v il
16 mb8116160a-60/MB8116160A-70 description the fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq1 to dq8 is latched on the falling edge of lcas and one appearing on the dq9 to dq16 is latched on the falling edge of ucas and the data is written into the memory. during the fast page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. fig. 10 ?fast page mode early write cycle (oe = ??or ?? ? or ?l t cas t pc t csh t rcd t rasp t cas t cp t rsh t rp t cas t rcd t cah t asc t cah t ar t asc t cah t asc col row add add col add col add t wcs t wch t wcs t wch t wcr t wch t wcs t ds t dh t ds t dh t dh t ds t dhr valid data valid data valid data ras v ih v il we v ih v il t rah t asr t crp a 0 to a 11 v ih v il dq (output) v oh v ol dq (input) v ih v il high-z lcas or ucas v ih v il
17 mb8116160a-60/MB8116160A-70 description the fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must me changed from low to high before we goes low (t oed + t t + t ds ). fig. 11 ?fast page mode delayed write cycle t asc ras v ih v il t rasp t csh t rcd t pc t rp t rsh t cas t cah t cwl t asc t cah t cas t ar t cp t rah t rcs t cwl t oeh t wp t ds t dh t dzc t on t oed t oeh t on t oed t ds t wp t rwl t wch t dh t oez t oez t on t dzo t on ? or ?l valid data row add col add col add valid valid we v ih v il a 0 to a 11 v ih v il dq (output) v oh v ol dq (input) v ih v il oe v ih v il t asr t cpr t wch high-z cas v ih v il
18 mb8116160a-60/MB8116160A-70 description during the fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. fig. 12 ?fast page mode read-modify-write cycle t asc ras v ih v il cas v ih v il we v ih v il t rcd t rpwc t rp t rwl t cwd t cah t asc t cah t cwd t rad t cp t rah t rcs t oeh t wcl t ds t dh t oed t ds t wp t wcl t dh t oez t oez t on t on t asr t crp row add col add col add valid valid t awd t wp t rcs t cpwd t dzc t rwd t cac t aa t on t oed t cac t aa t on t oea t oeh t oea t cpa ? or ?l valid data oe v ih v il a 0 to a 11 v ih v il dq (output) v oh v ol dq (input) v ih v il high-z t dzo t ras t rasp
19 mb8116160a-60/MB8116160A-70 a 0 to a 11 v ih v il v oh v ol ras v ih v il dq (output) fig. 13 ?ras -only refresh (we = oe = ??or ?? high-z row address t rc t ras t rp t rpc t rah t asr t crp t crp t off t oh description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 4096 row addresses every 65.6-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and ucas high throughout the cycle; the row address to be re- freshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. v oh v ol ras v ih v il dq (output) fig. 14 ?cas -before-ras refresh (addresses = we = oe = ??or ?? ? or ? description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. high-z t rc t ras t rp t rpc t chr t csr t cpn t off t oh ? or ? lcas or ucas v ih v il lcas or ucas v ih v il
20 mb8116160a-60/MB8116160A-70 a 0 to a 11 v ih v il v oh v ol ras v ih v il dq (output) fig. 15 ?hidden refresh cycle description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. we v ih v il oe v ih v il v ih v il dq (input) t rc t rc t ras t rp t ras t oel t rp t crp t chr t rsh t rcd t rad t rah t asr t asc t ral t ar t cah t rcs t rrh t cdd t aa t rac t cac t dzc t on t dzo t oea t oez t oed t off t oh high-z valid data out ? or ? row address column address high-z lcas or ucas v ih v il
21 mb8116160a-60/MB8116160A-70 a 0 to a 11 v ih v il v oh v ol ras v ih v il dq (output) fig. 16 ?cas -before-ras refresh counter test cycle we v ih v il oe v ih v il v ih v il dq (input) t crp ? or ? column addresses valid data high-z high-z valid data in high-z t rcd t cp t frsh t fcas t rp t fcah t asc t rcs t cwl t rwl t fcwd t fcac t ds t dzc t wp t dh t oed t dzo t oeh t on t oea t oez description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function of cas -before-ras refresh circuitry. if, a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are defined as follows: row address: bits a0 through a11 are defined by the on-chip refresh counter. column address: bits a0 through a7 are defined by latching levels on a0-a7 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows ; 1) initialize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ??to all 4096 row addresses at the same column address by using normal write cycles. 4) read ??written in procedure 3) and check; simultaneously write ??to the same addresses by using cas - before-ras refresh counter test (read-modify-write cycles). repeat this procedure 4096 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 4096 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). note: assumes that cas -before-ras refresh counter test cycle only. MB8116160A-70 mb8116160a-60 unit parameter min . max. ns no . min. max. 90 55 50 symbol (at recommended operating conditions unless otherwise noted.) cas to we delay time 91 35 ns 35 column address hold time cas pulse width 77 ns 70 99 ns 90 ns 90 99 access time from cas t fcac t fcah t fcwd t fcas t frsh ras hold time 92 93 94 lcas or ucas v ih v il
22 mb8116160a-60/MB8116160A-70 cas v oh v ol ras v ih v il v ih v il dq (output) fig. 17 ?self refresh cycle (a0-a11 = we = oe = ??or ?? ? or ? description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. if cas goes to ??before ras goes to ??(cbr) and the condition of cas ??and ras ??is kept for term of t rass (more than 100 m s), the device can enter the self refresh cycle. following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during ?as = l?and ?as = l? exit from self refresh cycle is performed by togging ras and cas to ??with specified t chs min.. in this time, ras must be kept ? with specified t rps min.. using self refresh mode, data can be retained without external cas signal during system is in standby. restriction for self refresh operation; for self refresh operation, the notice below must be considered. 1) in the case that distributed cbr refresh are operated between read/write cycles self refresh cycles can be executed without special rule if 4,096 cycles of distributed cbr refresh are executed within t ref max.. 2) in the case that burst cbr refresh or distributed burst ras -only refresh are operated between read/write cycles 4,096 times of burst cbr refresh or 4,096 times of burst ras -only refresh must be executed before and after self refresh cycles. high-z t oh t off t cpn t csr t rass t rps t rpc t chs a0 to a11, we , oe = ? or ? ras v ih v il * read/write operation can be performed non refresh time within t ns or t sn. read/write operation self refresh operation read/write operation t rass t ns <4 ms t sn < 4 ms 4,096 burst refresh cycle 4,096 burst refresh cycle MB8116160A-70 mb8116160a-60 unit parameter min . max. m s no . min. max. 100 symbol (at recommended operating conditions unless otherwise noted.) ras precharge time 101 125 ns 110 cas pulse width cas hold time ?0 ns ?0 t rass t rps t chs 100 102 note: assumes self refresh cycle only 100
23 mb8116160a-60/MB8116160A-70 n package dimensions (suf?: -pj) c 1995 fujitsu limited c42001s-2c-1 "a" 27.300.13(1.075.005) 25.40(1.000)ref 1.270.13 (.050.005) index 10.16 nom (.400) 10.970.13 (.432.005) 2.50(.098)nom 0.10(.004) 1 21 22 42 0.430.10(.017.004) 0.81(.032)max. details of "a" part 2.75(.108)nom 0.64(.025)min r0.81(.032)typ 9.400.51 (.370.020) 0.20 +0.05 ?0.02 +.002 ?.001 .008 .134 ?.008 +.014 ?0.20 +0.35 3.40 lead no * 42 pin, plastic soj (lcc-42p-m01) dimensions in mm(inches).
24 mb8116160a-60/MB8116160A-70 n package dimensions (continued) (suf?: -pftn) 1.150.05(.045.002) (.010) (.006) 0.25 0.15 (.005.002) 0.1250.05 * "a" 0.40(.016)max 0.15(.006)max details of "a" part 0.500.10 (.020.004) 10.760.20 (.424.008) 11.760.20 (.463.008) 10.160.10 (.400.004) 19.20(.756)ref 0.10(.004) 0.80(.031)typ 0.05(.002)min (stand off) 0.13(.005) m 0.300.10 (.012.004) 20.950.10(.825.004) lead no. index 25 15 11 1 26 36 40 50 1994 fujitsu limited f50006s-2c-1 c 50 pin, plastic tsop(ii) (fpt-50p-m06) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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